\begin{figure}%[htbp]
	\centering
%	\includegraphics[width=12cm]{Images/vfat}
%	\includegraphics[width=12cm]{Images/vfat_complete}
	\includegraphics[width=12cm]{Images/chip/scheme}
	\caption{Block diagram of the VFAT2 chip \cite{lhc-tot}} %\cite{vfat-man}}
	\label{vfat}
\end{figure}
\textbf{VFAT2} is the front-end electronics developed for the TOTEM experiment at the LHC. This ASIC (\textit{Application Specific Integrated Circuit}) converts the signals from the detectors into digital data through an amplifier-shaper-comparator chain.\\

The readout chips used during the test-beam were VFAT2 chips as well, since one of the aims of the test was a compatibility check between large capacitance pad-based readout systems and the TOTEM front-end electronics.\\

VFAT2 features a \textit{transimpedance} preamplification step ($V_{OUT} \propto I_{IN}$), whose output is sent to a shaper, and then compared to a customizable threshold potential. The latter is programmable in terms of \textit{VFAT2 DAC step bins}\footnote{Each \textit{VFAT2 DAC step bin} corresponds to $3.3mV$, that is an input charge of about $0,045fC \approx 281 e^-$.}. A feature named \textit{TrimDAC} allows us to set different thresholds for each channels, optimizing therefore the process of data acquisition even in noisy environments; however, we did not use this feature during the tests.\\

The monostable block then synchronizes the output of the comparator, providing by default a $1clk$ pulse for each threshold-crossing signal.\\

A \textit{Fast-OR} logic provides an \texttt{OR} of the monostable outputs of a programmable number of channels in just one clock cycle. This so-called \textit{S-Bit} can then be used as a trigger, making the VFAT2 an autotriggering front-end chip.\\
\begin{figure}
	\centering
	\subfigure[Fast-OR logic combining the monostable outputs to provide a trigger signal within one clock cycle \cite{tot-tdr}]
	{\includegraphics[width=12cm]{Images/chip/fastor}\label{fastor}}
	\vspace{2mm}
	\subfigure[Signal shaping for $MSPL=1clk$ \cite{vfat-man}]
	{\includegraphics[width=12cm]{Images/chip/vfat-mspl-op}\label{mspl-op}}
	\caption{Fast trigger and shaping features of VFAT2 chips}
\end{figure}

	\subsection*{Threshold}
It is necessary to set a threshold in order to prevent undesired hits\footnote{A \textit{hit} will be later defined as a channel that overcomes the threshold.} (i.e. noise) that would affect our data. VFAT2 allows to set both positive and negative thresholds, by changing the values of two registers $V_{T1}$ and $V_{T2}$:
% as shown in \tablename~\vref{setth} \cite{vfat-man}.\\
\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline \rule[-2ex]{0pt}{5.5ex} \textbf{Positive threshold} & $V_{T1} = 0$ & $V_{T2} = variable$ \\ 
	\hline \rule[-2ex]{0pt}{5.5ex} \textbf{Negative threshold} & $V_{T1} = variable$ & $V_{T1} = 0$ \\ 
	\hline 
	\end{tabular} 
	\caption{Threshold settings in VFAT2}
	\label{setth}
\end{table}

The threshold is then computed as $V_{TH} = V_{T2} - V_{T1}$.\\

Most of our scans were run at $th = -60ds$ (where $ds$ stands for \textit{VFAT2 DAC step bin}). Threshold scans were performed as well, to see at what level the noise starts to become significant: see \chaptername~\vref{ch-thscan}.

	\subsection*{Latency}
Given a trigger signal, we define \textbf{latency} the number of SRAM locations the chip has to go back in order to read the digital output of the event corresponding to that trigger. It is measured in clock periods, as it represents the elapsed time between the arrival of the trigger and the preceding storage of the corresponding event in the VFAT2 SRAM.\\

The latency of our setup was found to be $lat = 17clk$ when working with Ar/CO\subscript{2} 70/30, and $lat = 18clk$ when working with Ar/CO\subscript{2}/CF\subscript{4} 60/20/20.

	\subsection*{Monostable settings}
A signal can have either a thin or a large time distribution of charge (\textit{jitter} effect); the preamplifier stage preserves its $\dfrac{amplitude}{width}$ ratio. The monostable block allows to stretch its output pulse, which can be programmed to be as long as $1$ to $8$ clock periods. Stretching the monostable pulse generally decreases the time performance, as a subsequent signal may cross the threshold while the monostable output is still high. This would result in a single pulse instead of two, which would stay high for $n$ more clock cycles after the last threshold crossing, $1 \leq n \leq 8$.\\

However, stretching the monostable pulse allows us to find out whether two or more pulses are to be recognized as originated by the same event. Two undesired effects may happen indeed, which are countered by stretching the monostable output:\\
\begin{itemize}
	\item \textbf{Timewalk}: adjacent channels may be hit with different intensity (e.g. an electron avalanche falls over two adjacent pads): in this case, the channels which gather less charge may cross the threshold later than the other ones;
	\item \textbf{Jitter}: primary ionization clusters may be produced anywhere in the drift region, which has a significant thickness. Electrons released by the same incident particle at different heights in the drift region will thus reach the anode at different times; for a $3mm$ thick gap, and fields like those of \tablename~\vref{lg-gaps}, the arrival time spread of drifting electrons can reach $60 ns$.\label{jitter}
\end{itemize}

By stretching the monostable we can then synchronize several detectors being crossed by the same particle. In addition, a single latency value would allow us to retrieve the signals produced by all the tracks, despite possible timewalk-jitter delays.